Beirit Harvey

In just a few sharp strokes at CES, Dr. Su made it clear that AMD isn’t merely catching up to NVIDIA but working to redefine the battlefield. 

Dr. Lisa Su’s CES 2026 Keynote, In Plain English

Dr. Lisa Su’s keynote speech kicking off CES didn’t feel like a “here are some chips” update. In just a few sharp strokes at CES, Dr. Su made it clear that AMD isn’t merely catching up to NVIDIA but working to redefine the battlefield. 

Her keynote underscored that AMD is delivering not just competitive chips, but a whole new paradigm of open, scalable AI infrastructure. In other words, AMD is positioning itself as the architect of a more flexible and high-performance AI future where the rules 

Dr. Lisa Su’s keynote speech kicking off CES didn’t feel like a “here are some chips” update. In just a few sharp strokes at CES, Dr. Su made it clear that AMD isn’t merely catching up to NVIDIA but working to redefine the battlefield. 

Her keynote underscored that AMD is delivering not just competitive chips, but a whole new paradigm of open, scalable AI infrastructure. In other words, AMD is positioning itself as the architect of a more flexible and high-performance AI future where the rules are no longer dictated by a single player. It’s a shift that spells out a new era of choice and innovation in AI and one that TensorWave is ready to meet head-on.


The Big Cloud Moment: Helios

AMD put the spotlight on Helios, a rack-scale design meant to behave like one giant machine, not a pile of servers. The rack is built around a modular tray concept and is designed with real deployment concerns in mind, things like maintainability and reliability, while still aiming at massive scale.

At a high level, the architecture ties trays together using an accelerator link carried over Ethernet so dozens of accelerators in one rack can act as a single pool, and then scales outward using Ultra Ethernet NICs and DPUs.


What’s Inside Helios

AMD introduced Instinct MI455X and paired it with the next EPYC generation (“Venice”), plus Pensando networking, with liquid cooling in the design.

MI455X was described with a few headline hardware points (including HBM4 capacity and a multi-chiplet build), and Venice was positioned as a CPU explicitly engineered to keep these accelerators fed at rack scale (including a 256-core top-end configuration and higher memory/GPU bandwidth vs. the prior generation).

AMD also put rack-level numbers on the table; performance, total HBM capacity, and scale-up/scale-out bandwidth, and said Helios is targeted to ship later in 2026.


A Useful Reality Check From OpenAI: Demand Isn’t The Issue

OpenAI’s Greg Brockman basically reinforced the same point from the application side: they’ve been ramping compute aggressively and still run into internal tradeoffs because there’s never enough capacity to do everything they want at once.

He also talked about the split between instant, interactive experiences and continuous “background” agent workloads, two different operating modes that push hardware in different directions.


Proof Points: Why This Much Compute Matters

AMD brought in real workloads, not just benchmarks. Luma AI said a majority of its inference runs on AMD today and highlighted how video-style multimodal inference explodes “token-like” workload size; making cost and efficiency non-negotiable.

They also mentioned their major expansion is tied to MI455-class infrastructure.

AMD also reiterated its “open stack” posture; ROCm + broad framework/tool support, positioning software enablement as core to adoption, not an afterthought.


PCs: AI Moves From “Cloud Feature” To “Personal Default”

On the client side, AMD announced Ryzen AI 400 and emphasized near-term availability (first systems shipping this month, with a wide OEM ramp this year).

The key spec they highlighted was up to 60 TOPS from the NPU, alongside updated CPU/GPU cores.


A Quick Look Forward: MI500 In 2027

Finally, AMD previewed MI500 for 2027 (CDNA 6, 2nm, HBM4E) as the next big step on their accelerator roadmap. 


The Bigger Picture 

CES made the direction clear: the next wave of AI performance comes from well-designed systems; rack-scale compute, high-bandwidth networking, and software that’s ready to run real workloads. 

That’s exactly where TensorWave is focused: making AMD-powered infrastructure feel straightforward in production, from onboarding and migration through to tuning and steady-state operations, so teams can spend less time fighting the stack and more time shipping.


About TensorWave

TensorWave is the AI neocloud purpose-built for performance. Powered exclusively by AMD Instinct™ Series GPUs, we deliver high-bandwidth, memory optimized infrastructure that scales with your most demanding models–training or inference. 

Ready to get started? Connect with a sales engineer. 

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Dr. Lisa Su’s CES 2026 Keynote, In Plain English

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