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Beirit Harvey

Explore AMD CDNA 5, the architecture behind MI455X and Helios, including HBM4, higher memory bandwidth, low-precision compute, and rack-scale connectivity.

Inside AMD CDNA 5: The Architecture Powering MI455X and Helios

AMD’s CDNA 5 architecture marks a shift from simply building faster GPUs to designing AI infrastructure that can perform efficiently at rack scale.

As models grow and inference workloads become more demanding, GPUs need to move enormous amounts of data between memory, compute engines, and other accelerators. Memory capacity, bandwidth, data movement, and GPU-to-GPU communication can all affect how efficiently that compute is actually used. AMD’s CDNA 5 architecture was designed around these challenges.

CDNA 5 powers the AMD Instinct™ MI400 Series, including the MI455X GPU at the center of the AMD Helios rack-scale solution. Compared with previous generations, it introduces significant changes across compute, memory, data movement, and scale-up connectivity.

This blog breaks down some of the most important changes.


More Memory and Nearly 3x the Bandwidth

According to AMD, one of the biggest upgrades in CDNA 5 is the memory system. AMD Instinct MI455X includes 432 GB of HBM4 memory with up to 23.3 TB/s of peak memory bandwidth. By comparison, the previous-generation MI355X provides 288 GB of HBM3E and up to 8 TB/s. That gives MI455X 50% more high-bandwidth memory capacity and nearly three times the peak memory bandwidth.

That matters because modern AI workloads are increasingly memory intensive. Large models require space for weights, activations, and KV caches, while longer context windows and higher-concurrency inference can increase those requirements even further.

More capacity gives workloads additional room for this data in local HBM, while higher bandwidth helps keep the GPU’s compute resources supplied with data.


CDNA 5 Changes How Data Moves

More bandwidth alone isn't enough. CDNA 5 also introduces architectural changes designed to move data more efficiently.

One of the biggest additions is the Tensor Data Mover (TDM). It enables direct asynchronous transfers from global memory to local data share (LDS) without requiring data to first be staged through registers.

CDNA 5 also introduces L2 multicast, allowing data from a single memory request to be distributed to multiple Work Group Processors instead of repeatedly fetching the same information.

The underlying idea is straightforward: reducing unnecessary data movement can leave more GPU resources available for useful computation. That's increasingly important for AI workloads where moving data can become as important as performing the math itself.


A New Compute Architecture

The MI455X contains eight CDNA 5 compute chiplets alongside dedicated I/O and fabric/cache dies, with 192 MB of global L2 cache. Across the GPU, CDNA 5 provides 256 Work Group Processors (WGPs) and introduces a redesigned WGP architecture.

One of the key changes is Wave32 execution, which AMD says reduces synchronization overhead and improves SIMD utilization. CDNA 5 also adds WGP clustering, allowing multiple WGPs to work together more efficiently on matrix operations.

These changes are important because peak compute only tells part of the performance story. The architecture also has to keep those compute resources supplied with data and efficiently occupied.


More Low-Precision AI Compute

CDNA 5 also expands support for the lower-precision formats increasingly used in AI workloads. The architecture supports formats including MXFP4, MXFP6, MXFP8, and FP8, along with new block-scaling capabilities.

Lower precision can reduce the amount of memory required to represent model data and decrease memory traffic while increasing the number of operations the GPU can process.

MI455X delivers up to 40.3 PFLOPS of peak OCP MXFP4 performance and 20.1 PFLOPS of peak OCP MXFP8 performance.

AMD says CDNA 5's advanced low-precision capabilities can provide up to four times the throughput of previous-generation AMD Instinct GPUs for supported operations. For large-scale inference, where throughput, memory use, and cost efficiency all matter, those improvements can become especially important.


MI455X Is Designed to Scale

Perhaps the biggest CDNA 5 story isn't what happens inside a single GPU. It's what happens when many GPUs work together.

Each MI455X provides up to 3.6 TB/s of bidirectional scale-up bandwidth. Within Helios, the GPUs are connected through a single-hop, all-to-all scale-up fabric using UALink over Ethernet (UALoE).

That connectivity is important because large AI models are often distributed across multiple accelerators. Techniques such as tensor parallelism require GPUs to continuously exchange data, making communication another potential performance bottleneck.

CDNA 5 therefore isn't designed only to make individual accelerators faster. It's designed to make large groups of accelerators work together more efficiently.


Helios Takes CDNA 5 to Rack Scale

AMD Helios brings 72 MI455X GPUs together with 6th Gen AMD EPYC™ CPUs, AMD Pensando™ networking, and the ROCm™ software stack.

Across those 72 GPUs, Helios provides 31 TB of HBM4 memory, approximately 1.67 PB/s of aggregate peak memory bandwidth, and up to 260 TB/s of aggregate scale-up bandwidth.

AMD positions this as a shared pod memory system, although each MI455X still has its own 432 GB of local HBM4 connected across the scale-up fabric. This is an important shift in how AI infrastructure is designed.

Rather than optimizing around an individual GPU or even an eight-GPU server, Helios creates a tightly connected 72-GPU scale-up domain. Compute, memory, networking, cooling, power, and software all have to work together. In that sense, the rack increasingly becomes the unit of AI compute.


What CDNA 5 Means for AI Infrastructure

The most interesting part of CDNA 5 isn't any single specification. It's where AMD is focusing its architectural improvements. More HBM accommodates increasingly memory-intensive workloads. More bandwidth helps feed compute resources faster. TDM and L2 multicast reduce unnecessary data movement. Low-precision formats increase AI compute density. And high-bandwidth scale-up connectivity allows dozens of accelerators to work together.

Together, these changes address a fundamental challenge in modern AI infrastructure: keeping increasingly powerful compute resources productive at scale.

The fastest GPU on paper isn't necessarily the fastest AI system. Performance increasingly depends on how efficiently compute, memory, networking, and software work together. CDNA 5 and MI455X show AMD addressing that challenge at the accelerator level. Helios takes the same approach across the entire rack.


Bringing AMD Helios to TensorWave

TensorWave is expanding its AI cloud platform with the AMD Helios rack-scale solution, powered by AMD Instinct MI455X GPUs.

Helios brings CDNA 5 compute, HBM4 memory, AMD EPYC CPUs, AMD Pensando networking, and ROCm together in a platform designed for high-volume inference and frontier-scale AI workloads.

For TensorWave customers, that means access to AMD infrastructure designed not simply around more GPU compute, but around the memory, data movement, and connectivity requirements that increasingly determine AI performance at scale.


TensorWave Cloud: Engineered for AI Velocity

TensorWave is the industry’s premier AMD-exclusive cloud provider, delivering memory optimized AI infrastructure for training, fine-tuning and inference. 

Our platform combines the raw computational power of AMD's latest GPU architectures with innovative liquid cooling technology and ultra-high-speed networking, creating an optimized environment for the most demanding AI workloads. From large language model training to real-time inference, TensorWave provides the performance, scalability, and cost-efficiency that modern AI initiatives demand.

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Inside AMD CDNA 5: The Architecture Powering MI455X and Helios

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